It is known that a flash EEPROM cell is a memory cell that can be electrically programmed and electrically erased. The cell comprises source and drain electrodes, a floating gate and a control gate. Programming of the memory cell involves injection of hot electrons from the drain electrode into the floating gate, where the electrons get trapped. Erasure is achieved by means of Fowler-Nordheim tunneling of electrons from the floating gate normally to the source electrode.
Conventional flash EEPROM cells are stacked-gate devices wherein the floating gate is formed of a first level of polysilicon isolated from the semiconductor substrate by means of an oxide layer, and the control gate is formed of a second level of polysilicon isolated from the floating gate by means of a dielectric layer.
In order to fabricate flash EEPROM devices, manufacturing processes providing for two levels of polysilicon are necessary, and the number of additional masks with respect to a conventional CMOS manufacturing process is rather high.
Consequently, conventional flash EEPROM devices are rather costly.
In view of the state of the art described, it is an object of the present invention to provide a flash EEPROM memory cell which is simpler and cheaper to be fabricated that conventional flash EEPROM cells.